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Graphene Devices

Graphene Devices

Devices with electrical contacts are required for many aspects of graphene research. These so called graphene field effect transistors (GFETs) have been fabricated and characterized by AMO since 2005. For our standard GFETs exfoliated graphene on thermally oxidized silicon is used. The electrical contacts are fabricated by contact lithography and sputter deposition of nickel using the lift-off process. The highly doped silicon substrate with the thermal oxide layer is used as back-gate for control of the charge carrier density.

Besides, a wide spectrum of further CMOS typical process technologies and materials is available in our cleanroom. This allows the fulfillment of nearly any customer requirement. Please find an overview of alternative substrates, contact metals and dielectrics in the table below. We are pleased to advise and assist you with your tailored solution. Please contact our graphene team at szafranek(at)amo.de.

 

Substrate 

Graphene Structuring 

Metals for Contacts and Gate 

Lithography
Procedure 

Dielectrics e.g. for Top Gate

See Substrate 

Unstructured graphene flakes 

Nickel 

Optical Lithography:
min. structure with >1µm

Al2O3

Substrates can be sawn to the required size:
3*3 mm² -
6“ wafers

Structuring with oxide plasma and lithographical etch mask 

Titan/
Gold 

E-Beam Lithography: min. structure widths >50 nm 

 SiO2

Wolfram  

 

 

 

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