The transition from micro- to nano-scale CMOS is the major challenge for the semiconductor industry for the next decades. MOS transistors for the 65nm node in 2007 will have gate lengths of around 25nm. Simple downscaling of device dimensions will no longer be sufficient to achieve these ambitious goals set by the Semiconductor Industry Association. Non-classical multi-gate devices such as Triple-Gate MOSFETs, FinFETs or Gate-All-Around (GAA) FETs on silicon on insulator substrate (SOI) have been proposed as candidates to solve some of the challenges associated with nanoscale MOSFETs: control of short channel effects, increase of on-currents and threshold voltage control.
Researchers at AMO have developed an exploratory process for triple-gate MOSFETs on SOI, with one gate on top and two gates on the sides as shown in the scanning electron microscope image in Fig. 1. These three gates define the gate width. Furthermore, the devices have multiple wires to match on-currents of n- and p-MOS for CMOS integration. This is achieved by choosing an adequate number of parallel channels. To fabricate triple-gate MOSFETs, an E-beam defined structure (mesa) is etched into the top silicon of the starting SOI material. A gate oxide is then grown and a poly-silicon gate is deposited. In a next step, the gate is defined by E-beam lithography and etched by reactive ion etching. Finally, source, drain and gate are doped using ion implantation and rapid thermal annealing.
Short channel effects are effectively suppressed in triple-gate devices. Gate swing strongly decreases for devices with triple-gate geometry in contrast to planar (conventional) SOI MOSFETs fabricated on the same chip. The reduced gate swing directly translates to reduced off-state leakage currents. AMO has demonstrated that triple-gate MOSFETs are ideally suited for low power and low standby power digital applications.
Transistor drive-currents of triple-gate MOSFETs are considerably higher compared to planar SOI-MOSFETs, even for a smaller gate-overdrive. AMO's devices show excellent gate-driveability of triple-gate MOSFETs. This makes them prime candidates for future high performance digital circuits.
By combining the benefits of these triple-gate MOSFETs with the benefits of electrical-junction MOSFETs, AMO researchers have succesfully shown a path to the ultimately scaled transistor. Their 12nm device remains one of - if not the - smallest silicon transistor in Europe by now.
This project has been coordinated by AMO and financially supported by the German government (bmb+f) through Deutsches Zentrum für Luft- und Raumfahrt (DLR) under contract number 01 M 3101A. "Verbundprojekt: Hochgeschwindikeit-SOI-MOSFETs mit geringer Leistungsaufnahme (HSOI)"
